Recent improvements for DC-DC switching power supply circuits are increasingly important for use in portable and battery powered devices. Wide input voltage range and variable output voltages are increasingly important features for converters configured for automotive, computer and industrial applications. Recent deployment of USB 3.0 Power Driver devices also require high power in DC supply output voltages in order to power and also rapidly recharge USB coupled portable battery operated devices such as cellphones and tablets. In order to provide a particular output voltage to the system from a battery supply or other input voltage at a different voltage level, a buck-boost converter is often used. The buck-boost converter can provide a regulated and selectable or preconfigured output DC voltage when the input DC voltage is higher (buck mode) or lower (boost mode) than the output voltage. Wide input voltage ranges and a range of output voltages can be provided.
In a synchronous switching power converter, a clock signal at a more or less constant switching frequency is used to form a pulse to control switches, and the pulse width can be modulated (in pulse width modulation control, or “PWM)” to control the switching circuits. These PWM switching converter circuits are far more efficient and run cooler than the linear regulators used previously to provide, for example, a stepped up or stepped down DC-DC voltage.
In a buck mode operation, a first high side driver device (which may be, for example, a MOSFET transistor) is coupled with its current conduction path between an input voltage terminal and a first switching node. A pulse width modulated signal coupled to a gate terminal of the first high side driver device by a controller circuit is used to turn on or “close” the first high side driver in an “on” state, and the pulse width modulated signal is used to turn off or “open” the first high side driver in an “off” state. These two states can alternate in a more or less constant frequency pattern. The “duty cycle” of the switching converter is a ratio of the “on” time of the first high side switch to the “off” time. In the buck converter mode, an inductor is coupled between the first switching node and an output terminal for the output voltage. An output capacitor is coupled between the output terminal and a ground terminal. By closing the first high side driver for the “on” state time, and driving current into the inductor during the “on” state, and then subsequently opening the high side driver for the “off” state time, current flows into the inductor and into the load at the output, and an output voltage is developed across the load that is supported by the output capacitor. A rectifying device is also provided coupled between the first switching node and a ground potential. The rectifying device is used to supply current into the inductor when the first high side switch is open, the “off time” for the circuit. Increasingly this rectifying device is replaced by a first low side driver switch; although diode rectifiers are sometimes used. Use of a MOSFET transistor for both the first high side switch and the first low side switch (replacing the older diode rectifier) creates a synchronous switching converter topology.
In a boost mode operation, the input voltage at the input node is at a lower level than the desired output voltage. In this mode, the input voltage node is coupled to a first switching node at one side of the inductor. At the opposite side of the inductor, a second switching node is coupled to a second high side driver switch that selectively couples the output voltage node to the second switching node of the inductor. A second low side driver switch selectively couples the second switching node of the inductor to a ground terminal. The output capacitor described above is coupled between the output voltage node and ground. Typically the high and low side driver switches are implemented using MOSFET transistors, although in alternative arrangements other transistors and diodes can be used.
In operation, the boost mode provides a DC output voltage higher than the DC input voltage. This is accomplished by keeping the input voltage at the first switching node at one side of the inductor, and switching the high side driver between the second switching node at the opposite side of the inductor so that the second switching node is selectively coupled to the output voltage node. When the second high side driver is “on” (or the high side switch is closed), stored energy from the inductor is applied to the output voltage node, and the second low side driver is then alternatively switched on, thereby coupling the switching node of the inductor to ground, so that the inductor energy is not applied to the output node, and the output voltage is then provided by the output capacitor. By using the second high and second low side drivers in alternate cycles, and by controlling the pulse width that turns on the second high side driver, the output voltage can be regulated to a DC voltage that is greater than the input voltage or “boosted” above the DC input voltage.
As is known to those skilled in the art, in a switching buck-boost converter that uses a constant clocking frequency and a duty cycle with pulse width modulation to control the high and low side drivers, a transition occurs between buck mode and boost mode when the input voltage nears or is equal to the output voltage.
In prior known buck-boost converters, a problem arises in the transition zone. When the input voltage approaches the output voltage from either direction, the prior known solution converter enters a transition zone where the buck-boost converter is switching between buck and boost modes. In this operation, the on time and off time for certain switches in the circuit can be monitored. When the on time and off time are below minimum times (as indicated by a measurement of the pulse width output from a pulse width modulator), the converter switches back and forth from buck to boost and from boost to buck modes. In a condition where the input voltage is within a certain range of the desired output voltage, the converter may move erratically from buck to boost modes over adjacent clock cycles and may transition between the modes in an uncontrolled, erratic, or oscillating fashion. In some prior known circuits, the converter will further oscillate between buck and boost modes within a single clock cycle. This oscillation can cause noise and inefficiency in the converter operations. In certain cases an oscillating condition can exist that produces noise in an audible range, so that in an application where people can hear the audible switching noise, the use of the prior known buck-boost converters can be impractical or can be precluded by the undesirable audible switching noise produced by the converter.
FIG. 1 depicts, for the purpose of explanation, a circuit diagram of a typical buck-boost switching converter circuit 10 in a four switch configuration. In FIG. 1, a first high side driver Q1 is shown coupled between the first switch node SW1 and an input voltage VIN. In FIG. 1, the example implementation shows the first high side driver Q1 implemented with an N-type MOSFET that is sufficiently large to provide the required or expected load current to the corresponding inductor (labeled L_1) during the “on” state in buck mode. Further, in circuit 10, a first low side driver Q2, which in this example is also an N type MOSFET device, is coupled between the switch node SW1 and a ground terminal through a current sense resistor RS1. During the “off” state of the switching circuit 10 in a buck mode of operation, the first low side switch Q2 provides a current path from the ground terminal Vss to supply load current to the inductor L_1.
In FIG. 1, a second high side driver Q3 is coupled between the inductor switching node SW2 and the output node VOUT for supplying an output voltage to a load (not shown). During “off” states of boost mode operation, the high side driver Q3 will be active and acts as a rectifying device. The high side driver Q3 is another N-type MOSFET that is sufficiently large to provide the required or expected load current to the output node VOUT from the inductor L_1 during the “off” state of a boost mode operation. A second low side driver Q4 is coupled between the inductor switching node SW2 and the ground terminal Vss, and provides current to the inductor L_1 during the “on” state in a boost mode of operation.
In FIG. 1, four gate signals are used to control the operation of the buck-boost converter. The first high side driver MOSFET Q1 has a gate control signal HDRV1. The first low side driver MOSFET Q2 has a gate control signal LDRV1. The second high side driver MOSFET Q3 has a gate control signal HDRV2. A second low side driver MOSFET Q4 has a second gate control signal LDRV2 as an input. These control signals are pulse width modulated during the buck and boost operations.
To operate the buck-boost converter 10, these four gate control signals are provided by a synchronous switch control circuit. A clock signal with a switching frequency fs and a cycle length of l/fs is used to control the gate control signals. By modulating the pulse widths (PWM) of the gate control signals, the input voltage at node VIN and output voltage at node VOUT are coupled to the inductor L_1 in a manner to produce the desired DC output voltage from the DC input voltage. Using the four switch converter circuit of FIG. 1, this DC-DC voltage conversion can be done when the input voltage is less than the output voltage Vout in a boost mode of operation, and when the input voltage is greater than the output voltage the conversion can be performed in a buck mode of operation.
In operation, with the converter circuit 10 in FIG. 1 active, a feedback path can be formed, for example, to sense the output voltage (or the output current) at the node VOUT. When the output voltage is lower than the desired output voltage, the width of the pulses used to control the first high and first low side drivers Q1, Q2 in FIG. 1 can be varied using pulse width modulation (PWM) to control the switching buck boost converter 10. The output voltage at the node VOUT is then proportional to the duty cycle of the gate control signal HDRV1 coupled to the high side driver Q1. The longer the high side driver Q1 is turned on in each clock cycle for the synchronous converter in a buck mode of operation, the higher the output voltage at node VOUT will be. When the output voltage at the node VOUT is higher than desired, the pulse width is modulated to reduce the on time for the high side driver Q1 and also increase the off time, the time that the low side driver Q2 is active for each clock cycle, to allow the output voltage at the node VOUT to decrease.
FIGS. 2A and 2B depict, in simplified circuit diagrams, the buck mode operations of a four switch buck-boost converter 20. In FIG. 2A, buck boost converter 20 is shown in a high side driver “off” state of a buck mode of operation. During buck mode operations, as shown by the dark lines in FIG. 2A and FIG. 2B, the output node VOUT is always coupled to the inductor L_1 at the switching node SW2. The second high side driver (Q3 in FIG. 1) is therefore always “on” or active in the buck mode of operations. In the “off” state in the buck mode of operation illustrated in FIG. 2A, the inductor L_1 supplies current to the output capacitor (not shown in FIGS. 2A and 2B, but CO is shown in FIG. 1) at the output node VOUT. The output voltage VOUT from the converter 20 is therefore supplied by the output capacitor CO and the current from the inductor L_1. In the “off” state of the buck mode of operation, the first low side driver (Q2 in FIG. 1) is active while the first high side driver Q1 is turned off. This operation is indicated by the heavy black lines in FIG. 2A, indicating which components are active in the circuit 20 in the “off” state of the buck mode of operation, labeled TOFF1.
In FIG. 2B, the dark line illustrates the “on” state for the converter 20 in buck mode operations. In the buck mode “on” state, the input voltage VIN is coupled to the inductor L_1 at the switch node SW1 (by the first high side driver MOSFET Q1 in FIG. 1, for example), while the output node VOUT is always coupled to switch SW2 at the opposite side of inductor L_1 (by placing a high voltage at the gate terminal of the second high side driver Q3). In the “on” state for the buck mode, the input voltage at the node VIN is coupled to the switching node SW1 at one side of the inductor L_1 as shown in FIG. 1, and the output voltage node VOUT is coupled to the switching node SW2 at the other side of the inductor L_1. In this manner the output voltage at node VOUT is maintained by the input voltage at the node VIN, and the inductor L_1, which supplies current to charge the output capacitor CO (not shown) during the “on” state of buck mode operation. The dark lines in FIG. 2B show the current path for this mode, labeled TON1.
FIG. 2C illustrates, in a simplified timing diagram, the voltages at nodes SW1 and SW2 for the buck mode of operation of converter 20. Note that in the buck mode of operation, the output node VOUT is always coupled to the inductor L_1 at the switching node SW2. In FIG. 2C, the timing diagram illustrates the “off” time for the buck mode of operation when the first high side driver Q1 in FIG. 1 is off (and the low side driver Q2 is “on” or active and acts as a rectifier device), shown by the switching action at the switching node SW1 coupled to the inductor L_1. The time “TOFF1” is the time when the low side driver Q2 in FIG. 1 is active in each clock cycle.
During each clock cycle, for signal CLK, node SW1 is at a high voltage (the input voltage at the node VIN) and at a low voltage (the ground potential) in alternating portions of the clock cycle. This action is accomplished by controlling the high side driver MOSFET Q1 and the low side driver MOSFET Q2, using the gate control signals HDRV1 and LDRV1 shown in FIG. 1 in a synchronous manner using pulse width modulation.
In FIGS. 3A and 3B, a simplified circuit diagram illustrates the operation of the buck-boost converter 30 (such as converter 10 shown in FIG. 1) in boost mode. In boost mode, the input voltage at the node VIN is lower than the output voltage desired at the output node VOUT. In boost mode, the input voltage VIN is always coupled to the switching node SW1. In boost mode the output node VOUT is alternatively coupled to, and then not coupled to, the switching node SW2. In FIG. 3A, the converter 30 is shown with the low side driver Q4 in FIG. 1 “on” shown as the time TON2, and thus the output voltage node VOUT is not connected to the inductor L_1 at the switching node SW2.
FIG. 3B illustrates the boost mode of operation when the output node VOUT is coupled to the switching node SW2. This happens in the TOFF2 condition, when the low side driver Q4 in FIG. 1 is off, the high side driver Q3 is active, and the output voltage node VOUT is coupled to the inductor switching node SW2. By controlling the amount of time that the high side driver MOSFET Q3 and the low side driver Q4 are active using the gate control signals HDRV2, LDRV2 in pulse width modulation, the output voltage at the node VOUT can be controlled.
FIG. 3C illustrates the boost operation in a simplified timing diagram of the voltage at the switch nodes SW1 and SW2. For each clock cycle, the duty cycle is used to control the time the low side driver Q4 is active, and the time the high side driver Q3 is on, to control the MOSFET driver transistors in the boost mode of operation. Pulse width modulation is used to vary the duty cycle of the high side and low side driver transistors to control the output voltage VOUT.
In the prior known solutions, the buck boost converter transitions between buck and boost modes based on the duration of the control signals TOFF1 and TON2. When operating in buck mode, a circuit controller determines if the pulse duration time TOFF1 is less than a predetermined minimum time, indicating that the input voltage is very close to the output voltage and that the maximum duty cycle for the pure buck operation is exceeded. When the condition is met, a flag called “Tmin” is set and the converter transitions to boost mode. Similarly, in boost mode, the controller determines if the pulse duration time TON2 is less than a minimum, indicating the input voltage is very close to the output voltage, and thus the minimum boost duty cycle is exceeded, and when the condition is met as indicated by the flag “Tmin” the controller transitions to buck mode.
FIG. 4 illustrates the modes of operation of a buck-boost converter in a graph that plots input voltage VIN, and the output voltage VOUT as voltage shown on the vertical axis, and plots time on the horizontal axis. The graph illustrates that the converter operates in buck mode when the input voltage is greater than the output voltage, shown as VIN>VOUT starting at the left side of the graph near the vertical axis, the converter operates in boost mode as illustrated at the right side of the figure, when the input voltage is less than the output voltage shown as VIN<VOUT at the right side of the graph, and in the center of FIG. 4, the converter enters a transition region when VIN is approximately equal to, or close, to the voltage of VOUT.
The transition operation of a converter control circuit of the prior known solutions is shown in FIG. 5. In FIG. 5, a two state converter control configuration 50 is shown. When the converter 50 is operating in the buck mode, in the state numbered 51 labeled BUCK, and the condition “TON2,min” indicates that the pulse duration time TOFF1 is less than a predetermined time duration, then the converter can no longer operate in only in pure buck mode (as the maximum duty cycle has been reached), and the converter then transitions to a boost mode of operation in a state labeled BOOST, numbered 53. When in the boost mode in state 53, when the condition “TON2,min” is met, the converter 50 transitions back to the buck mode 51. When the input voltage VIN is very close to or equal to the output voltage VOUT, the minimum conditions (referred to together as “Tmin”) can be true each clock cycle, and the prior known converter 50 can go into an oscillation mode where it irregularly makes transitions between the two states 51 and 53, and this creates inefficiency, and random switching noise. Further, the transitions between the two states 51 and 53 can even occur within a single clock cycle. Because the transitions between buck and boost modes are not regular, noise filtering to reduce the switching noise is particularly difficult for a prior known buck-boost converter operating in this transition mode.
FIG. 6 depicts in a simulation plot of selected signals during an operation of a prior known buck-boost converter in a transition mode. In FIG. 6, the top trace labeled “VOUT” illustrates the ripple on the voltage output node, showing the effect of the frequent transitions between buck and boost mode on the output signal. The voltage at the switching node SW1 is depicted on the second trace from the top in FIG. 6. The voltage at the switching node SW2 is depicted on the third trace from the top in FIG. 6. The current flowing in the inductor L_1 is shown in the bottom trace of FIG. 6, labeled IL_1. The voltages at the switching nodes SW1 and SW2 show the buck-boost converter transitioning irregularly between buck and boost modes of operation, creating inefficiency and producing transient switching noise as can be seen in the output voltage VOUT.
Improvements in the operation of synchronous switching buck-boost converters are therefore needed to address the deficiencies and disadvantages of the known prior approaches.